Samsung S3C6400X, User Manual, Page: 208 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR CF CONTROLLER
9-21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ATA_CONTROL
Register Address Description Reset Value
ATA_CONTROL 0x70301900 ATA enable and clock down status 0x0000_0002
ATA_CONTROL Bits Description R/W Reset Value
Reserved [31:2] Reserved bits R 0x0
CLK_DOWN_READY [1] Status for clock down
This bit is asserted in idle state when
ATA_CONTROL bit [0] is zero.
0 : not ready for clock down
1 : ready for clock down
R 0x1
ATA_ENABLE [0] ATA enable
0 : ATA is disabled and preparation for clock
down maybe in progress
1 : ATA is enabled.
When this value is set to 1, delay of 200ms will
be required.
R/W 0x0
ATA_STATUS
Register Address Description Reset Value
ATA_STATUS 0x70301904 ATA controller status
0x0000_0000
ATA_STATUS Bits Description R/W Reset Value
Reserved [31:5] Reserved bits R 0x0
ATADEV_IRQ [4] ATAPI interrupt signal line R 0x0
ATADEV_IORDY [3] ATAPI iordy signal line R 0x0
ATADEV_DMAREQ [2] ATAPI dmareq signal line R 0x0
XFR_STATE [1:0] Transfer state
2’b00 : idle state
2’b01 : transfer state
2’b11 : wait for completion state
R 0x0