Samsung S3C6400X, User Manual, Page: 160 / 1189

PRELIMINARY
ONENAND CONTROLLER S3C6400X RISC MICROPROCESSOR
7-30
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INTERRUPT MONITOR CYCLE REGISTER
Register Address R/W Description Reset Value
INT_MON_CYC0
INT_MON_CYC1
0x701001B0
0x701801B0
R/W Bank0 Interrupt Monitor Cycle Count Register 0x01F4
INT_MON_CYCn Bit Description Initial State
Reserved [31:12] 0
INT_MON_CYC [11:0] Sets the number of cycles in between checks of the
INT_ERR_STAT register and the memory device’s status
register. This register is only used if the Flash configuration
register bit IOBE is clear. 500
ACCESS CLOCK REGISTER
Register Address R/W Description Reset Value
ACC_CLOCK0
ACC_CLOCK1
0x701001C0
0x701801C0
R/W Bank0 Access Clock Register 0x0003
ACC_CLOCKn Bit Description Initial State
Reserved [31:3] 0
ACCESS_CLK [2:0] Sets the number of cycles required to cover the access time of
the Flash memory device. Follows the formula
(35ns/(Xm0SMCLK 1).
Flash Core
Clock (MHz)
Interface Clock (MHz) ACCESS_CL
K
133 66.5 3
100 50 2
60 30 2
3
SLOW READ PATH REGISTER
Register Address R/W Description Reset Value
SLOW_RD_PATH0
SLOW_RD_PATH1
0x701001D0
0x701801D0
R/W Bank0 Slow Read Path Register 0x0000
SLOW_RD_PATHn Bit Description Initial State
Reserved [31:1] 0
SRP [0] Delays the read data capture by 1/2 cycle to accommodate
the board delay. Default is 0x0. 0