PRELIMINARY
USB2.0 HS OTG
S3C6400X RISC MICROPROCESSOR
26-22
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
GUSBCFG
Bit
R/W
Description
Initial State
[31:16]
Reserved
16’h0
PHY Low-Power
Clock Select
[15]
PHY Low-Power Clock Select
Selects either 480-MHz or 48-MHz (low-power) PHY
mode. In FS and LS modes, the PHY can usually
operate on a 48-MHz clock to save power.
·
1’b0 : 480-MHz Internal PLL clock
·
1’b1 : 48-MHz External clock
*Note : This bit must be configured with
OPHYPWR.pll_powerdown.
1’b0
[14:10]
Reserved
4’h5
HNPCap [9]
R_W
HNP – Capable
The application uses this bit to control the OTG
cores’s HNP capabilities.
·
1’b0 : HNP capability is not enabled
·
1’b1 : HNP capability is enabled
1’b0
SRPCap [8]
R_W
SRP – Capable
The application uses this bit to control the OTG
core’s SRP capabilities.
·
1’b0 : SRP capability is not enabled
·
1’b1 : SRP capability is enabled
1’b0
[7:4]
Reserved
4’h0
PHYIf [3]
R_W
PHY
Interface
The application uses this bit to configure the core to
support a UTMI+ PHY with an 8- or 16-bit interface.
Only 16-bit interface is supported. This bit must be
set to 1.
·
1’b0 : 8 bits
·
1’b1 : 16 bits
1’b0
TOutCal
[2:0]
R_W
HS/FS Timeout Calibration
Set this bit to 3’h7.
3’h0
CORE RESET REGISTER (GRSTCTL)
The application uses this register to reset various hardware features inside the core.
Register
Address
R/W
Description
Reset Value
GRSTCTL
0x7C00_0010
R/W
Core Reset Register
32 bits
GRSTCTL
Bit
R/W
Description
Initial State