PRELIMINARY
PRODUCT OVERVIEW
S3C6400 RISC MICROPROCESSOR
1-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1.1.16.3 TrustZone Interrupt Controller
Provides a software interface to the secure interrupt system in a TrustZone design
nFIQ generation, under secure control, from any system interrupt source
Masking of chosen nFIQ interrupt from non-secure interrupt controller
1.1.16.4 TrustZone Protection Controller
Provides a software interface to the protection bits in a secure system in a TrustZone design
Protection bits to enable programming of up to 24 areas of memory as secure or non-secure
AMBA APB interface
1.1.16.5 Timer with PWM (Pulse Width Modulation)
4-ch 32-bit Timer with PWM
1-ch 32-bit internal timer with DMA-based or interrupt-based operation
Programmable duty cycle, frequency, and polarity
Dead-zone
generation
Support external clock source
1.1.16.6 16-bit Watchdog Timer
Interrupt request or system reset at time-out
1.1.16.7 RTC (Real Time Clock)
Full clock features: msec, sec, min, hour, day, week, month, year
32.768 KHz operation
Alarm
interrupt
Time-tick
interrupt
1.1.17 System Management
The S3C6400 microprocessor provides the following System Management features:
Little Endian format support
1.1.18 System Operating Frequencies
The S3C6400 microprocessor provides the following System Operation Frequencies features:
ARM1176JZF-S core clock rate maximum is 667MHz@ TBD V
System operating clock generation
o
Three on-chip PLLs, APLL, MPLL & EPLL
o
APLL generates an independent ARM operating clock
o
MPLL generates the system reference clock
o
EPLL generates clocks for peripheral IPs
Power Management
Clock-off control for individual components
Various power-down modes are available such as Idle, Stop and Sleep mode
Wake-up by one of external interrupts or by various interrupt sources. Refer system controller manual.