PRELIMINARY
S3C6400X RISC MICROPROCESSOR
SECURITY SUB-SYSTEM
13-21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SECURITY SUB-SYSTEM SHA-1/PRNG MODULE
HASH_CONTROL
Register
Address
R/W
Description
Reset Value
HASH_CONTROL
0x7D30_0000 R/W Hash engine control register
0x0000_0000
HASH_CONTROL
Bit
Description
Initial State
Reserved [31:9]
Reserved
0x0000_00
USE_IV [8]
Use arbitrary IV instead of SHA-1 constants
0: constants
1: arbitary IV,
0b
End_of_Hash_byte [7:6]
End of the SHA text byte
00 : first byte (LSB in 32bit)
01 : second byte
10 : third byte
11 : fourth byte (full 32bit)
00b
SEED_SETTING_ENABLE
[5]
Seed setting enable (1’b1)
0b
Hash_input_finished
[4]
Finished the hash input (will be cleared by hardware)
0b
Hash_start [3]
Start the hash (software reset) (will be automatically
cleared by hardware)
0b
Data_Selection [2]
Indicates whether the next data of register values are keys
or text
0:
text
1:
key
0b
Engine_Selection [1:0]
To use as SHA-1 or HMAC or PRNG
00:
HMAC
01:
SHA1
10: PRNG
11 = reserved
00b
HASH_DATA
Register
Address
R/W
Description
Reset Value
HASH_DATA
0x7D30_0004 R/W Hash
data
0x0000_0000
HASH_DATA
Bit
Description
Initial State
HASH_DATA
[31:0]
Hash data input register ( HASH_CONTROL[5] == 1’b0)
0x0000_0000