PRELIMINARY
USB2.0 HS OTG
S3C6400X RISC MICROPROCESSOR
26-66
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
exhausted the transfer size amount of data. The
transfer size can be set to the maximum packet size
of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet is
read from RxFIFO and written to the external
memory.
DEVICE ENDPOINT-n TRANSFER SIZE REGISTER (DIEPTSIZn/DOEPTSIZn)
Endpoint_number: 1
≤
n
≤
15
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using
endpoint Enable bit of the Device Endpoint-n Control registers, the core modifies this register. The application can
only read this register once the core has cleared the Endpoint Enable bit. This register is used only for endpoints
other than Endpoint 0.
Register
Address
R/W
Description
Reset Value
DIEPTSIZn
/
DOEPTSIZn
0x7C00_0910
+n*20h /
0x7C00_0B10
+n*20h
R/W
Device Endpoint-n Transfer Size Register
32 bits
DIEPTSIZn/
DOEPTSIZn
Bit
R/W
Description
Initial State
[31]
Reserved
1’b0
Multi Count
Applies to IN endpoints only.
For periodic IN endpoints, this field indicates the
number of packets that must be transmitted per
microframe on the USB. The core uses this field to
calculate the data PID for isochronous IN endpoints.
·
2’b01 : 1 packet
·
2’b10 : 2 packets
·
2’b11 : 3 packets
R_W
RO
For non-periodic IN endpoints, this field is valid only
in Internal DMA mode. It specifies the number of
packets the core must fetch for an IN endpoint
before it switches to the endpoint pointed to by the
Next Endpoint field of the Device Endpoint-n Control
register.
MC
RxDPID
[30:29]
RO
Received Data PID
Applies to isochronous OUT endpoints only.
This is the data PID received in the last packet for
this endpoint.
·
2’b00 : DATA0
·
2’b01 : DATA1
2’b0