PRELIMINARY
S3C6400X RISC MICROPROCESSOR
USB2.0 HS OTG
26-3
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MODES OF OPERATION
The application can operate the Link either in DMA mode or in Slave mode. The application cannot operate the
core using DMA and Slave modes simultaneously.
DMA Mode
USB OTG host uses the AHB Master interface to transmit packet data fetch (AHB to USB) and receive data
update (USB to AHB). The AHB master uses the programmed DMA address (HCDMAn register in Host mode and
DIEPDMAn/DOEPDMAn register in Device mode) to access the data buffers.
Slave Mode
USB OTG can operate either in transaction-level operation or in pipelined transaction-level operation. The
application handles one data packet at a time per channel / endpoint in transaction-level operations. In pipelined
transaction-level operation, the application can program the OTG to perform multiple transactions. The advantage
of pipelined operation is that the application is not interrupted on packet basis.
SYSTEM CONTROLLER SETTING
A register in SYSTEM CONTROLLER has to be set for USB to work appropriately.
OTHERS
Bit
R/W
Description
Initial State
USB_SIG_MASK
[16]
R_W
USB signal mask to prevent unwanted leakage
(This bit must be set before USB PHY is used.)
1’b0
The 16
th
bit of OTHER CONTROL register based on address 7E00_F900h is guided to be set differently
depending on the system operation mode:
Normal Mode
Initial state of USB_SIG_MASK is 1’b0. It must be set to 1’b1 in order to start USB transaction.
Stop/Deep Stop/Sleep Mode
In these operation modes, USB PHY or USB LINK power can be cut off.
Therefore to prevent unwanted leakage current , USB_SIG_MASK must be set to 1’b0 before entering these
modes.