Samsung S3C6400X, User Manual, Page: 1122 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR IRDA
38
-15
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IRDA INTERUPT IDENTIFICATION REGISTER(IRDA_IIR)
Register Address R/W Description Reset Value
IrDA _IIR 0x7F00_7010 R IrDA Interrupt Identification Register 0x00
IrDA _IIR Bit Description Initial State
Last byte to Rx FIFO [7] Last byte write to RX FIFO interrupt pending. When the
last payload byte of the frame is loaded into the RX FIFO,
bit 7 is set to ‘1’. Bit 7 is set prior to bit 2. Bit 7 is cleared
when it is read.
0
Error indication [6] Receiver line error Indication. Bit 6 is set to a ‘1’ if one of
three possible errors occurs in the RX process. With the
corresponding interrupt enable bit active, one of PHY,
CRC and Frame length errors let this bit go active. Bit 6 is
cleared when the source of the error is cleared.
0
Tx Underrun [5] Transmit under-run interrupt pending. When
corresponding interrupt enable bit is active, bit 5 is set to
‘1’ if an under-run occurs in TX FIFO. Bit 5 is cleared by
serving the under-run.
0
Last byte detect [4] Detects last byte of a frame interrupt pending. If the
corresponding interrupt enable bit is active, bit 4 is set to
‘1’ when the demodulation block detects the last byte of a
received frame and the CRC decoding is finished. Bit 4 is
cleared when it is read.
0
Rx overrun [3] RX FIFO over-run interrupt. When corresponding interrupt
enable bit is set, bit3 is active, bit 3 is set to ‘1’ when an
overrun occurs in the RX FIFO. Bit 3 is cleared by serving
the over-run.
0
Last byte read from Rx
FIFO
[2] RX FIFO last byte read interrupt. When corresponding
interrupt enable bit is active, it is set to ‘1’ when the CPU
reads the last byte of a frame from the RX FIFO. It is
cleared when it is read.
0
Tx FIFO below
threshold
[1] TX FIFO below threshold interrupt pending. Bit 1 is set to
‘1’ when the transmitter FIFO level is below its threshold
level.
0
Rx FIFO over threshold [0] RX FIFO over threshold interrupt pending. Bit 0 is set to ‘1’
when the receiver FIFO level is equal to or above its
threshold level.
0