PRELIMINARY
ELECTRICAL DATA
S3C6400X
RISC MICROPROCESSOR
41-24
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 41-12. Memory Interface Timing Constants (Mobile DDR)
(VDDINT= 1.0V
±
0.05V, TA = -40 to 85
°
C, VDDM1 = 2.5V
±
0.25V, 1.8V
±
0.15V )
Parameter Symbol
Min
Max
Unit
DDR SDRAM Address Delay
t
SAD
1.69 5.61 ns
DDR SDRAM Chip Select Delay
t
SCSD
2.09 5.27 ns
DDR SDRAM Row active Delay
t
SRD
1.88 4.67 ns
DDR SDRAM Column active Delay
t
SCD
1.63 3.96 ns
DDR SDRAM Byte Enable Delay
t
SBED
-0.06 0.02 ns
DDR SDRAM Write enable Delay
t
SWD
2.24 5.51 ns
DDR SDRAM Output data access time from CK
t
SAC
2.00 6.00 ns
DDR SDRAM Row Precharge time
t
RP 22.50 ns
DDR SDRAM RAS to CAS delay
t
RCD 22.50 ns
DDR SDRAM Write recovery time
t
WR 12.00 ns
DDR SDRAM Clock low level width
t
CL 3.38
4.12
ns
DDR SDRAM Read Preamble
t
RPRE
6.75 8.25 ns
DDR SDRAM Read Postamble
t
RPST
3.00 4.50 ns
DDR SDRAM Write Postamble time
t
WPST
3.00 4.50 ns
DDR SDRAM Clock to valid DQS-In
t
DQSS
5.63 9.37 ns
DDR SDRAM DQS-In Setup time
t
WPRES
1.30 ns
DDR SDRAM DQS-In Hold time
t
WPREH
1.30 ns
DDR SDRAM DQS-In high level width
t
DQSH
3.00 4.50 ns
DDR SDRAM DQS-In low level width
t
DQSL
3.00 4.50 ns
DDR SDRAM read Data Setup time
t
DDS
- 0.70 ns
DDR SDRAM output Data Delay
t
DDD
-0.05 0.26 ns
DDR SDRAM DQS Delay
t
DQSD
-0.30 0.83 ns