PRELIMINARY
PRODUCT OVERVIEW
S3C6400 RISC MICROPROCESSOR
1-4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1.1.2 Microprocessor
The ARM1176JZF-S processor incorporates an integer unit that implements the ARM11 ARM architecture v6. It
supports the ARM, Thumb™ instruction sets and Jazelle technology to enable direct execution of Java bytecodes,
and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The features of ARM1176JZF-S processor include:
z
TrustZone™ security extensions.
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High-speed
Advanced Microprocessor Bus Architecture
(AMBA)
Advanced Extensible
Interface
(AXI) level two interfaces supporting prioritized multiprocessor implementations.
z
Integer unit with integral EmbeddedICE-RT logic.
z
Eight-stage pipeline.
z
Branch prediction with return stack.
z
Low interrupt latency configuration.
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External coprocessor interface and coprocessors CP14 and CP15.
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Instruction and Data
Memory Management Units
(MMUs), managed using MicroTLB
structures backed by a unified Main TLB.
z
Instruction and data caches, including a non-blocking data cache with
Hit-Under-Miss
(HUM).
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Virtually indexed and physically addressed caches.
z
64-bit interface to both caches.
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Vector Floating-Point
(VFP) coprocessor support.
z
External coprocessor support.
z
Trace support