Samsung S3C6400X, User Manual, Page: 1073 / 1189

PRELIMINARY
S3C6400 RISC MICROPROCESSOR AC97 CONTROLLER
35-13
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
interrupt
MIC in channel overrun interrupt [19]
0 : Not requested 1 : Requested 0
PCM out channel threshold
interrupt [18]
0 : Not requested 1 : Requested 0
PCM in channel threshold
interrupt [17]
0 : Not requested 1 : Requested 0
MIC in channel threshold
interrupt [16]
0 : Not requested 1 : Requested 0
- [15:3] Reserved. 0x000
Controller main state [2:0]
000 : Idle 001 : Init 010 : Ready
011 : Active 100 : LP 101 : Warm
001
AC97 CODEC COMMAND REGISTER (AC_CODEC_CMD)
When you control writing or reading, you must set the Read enable bit. If you want to write data to the AC97
Codec, you set the index (or address) of the AC97 Codec and data.
Register Address R/W Description Reset Value
AC_CODEC_CMD 0x7F001008 R/W AC97 Codec Command Register 0x00000000
AC_CODEC_CMD Bit Description Initial State
-
[31:24] Reserved 0x00
Read enable [23] 0 : Command write
(1)
1 : Status read 0
Address
[22:16] Codec command address 0x00
Data [15:0] Codec command data 0x0000
Note:
When the commands are written on the AC_CODDEC_CMD register, It is recommended to have the delay time
between the command and the next command is more than 1 / 48KHz.
AC97 CODEC STATUS REGISTER (AC_CODEC_STAT)
If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid.
Register Address R/W Description Reset Value
AC_CODEC_STAT 0x7F00100C R AC97 Codec Status Register 0x00000000
AC_CODEC_STAT Bit Description Initial State
-
[31:23] Reserved. 0x00
Address
[22:16] Codec status address 0x00