PRELIMINARY
IIS-BUS INTERFACE
S3C6400X RISC MICROPROCESSOR
36-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IISFIC
Bit
R/W
Description
[31:16]
R/W
Reserved. Program to zero.
TFLUSH
[15]
R/W
TX FIFO flush command.
0: No flush, 1: Flush
[14:13]
R/W
Reserved. Program to zero.
FTXCNT
[12:8]
R
TX FIFO data count. FIFO has 16 dept, so value ranges from 0 to
16.
N: Data count N of FIFO
RFLUSH
[7]
R/W
RX FIFO flush command.
0: No flush, 1: Flush
[6:5]
R/W
Reserved. Program to zero.
FRXCNT
[4:0]
R
RX FIFO data count. FIFO has 16 dept, so value ranges from 0 to
16.
N: Data count N of FIFO
IISPSR
Register
Address
Description
Reset Value
IISPSR
0x7F00200C
0x7F00300C
IIS interface clock divider control register
0x0000_0000
IISPSR
Bit
R/W
Description
[31:16]
R/W
Reserved. Program to zero.
PSRAEN
[15]
R/W
Pre-scaler (Clock divider) A active.
0: Inactive, 1: Active
[14]
R/W
Reserved. Program to zero.
PSVALA
[13:8]
R/W
Pre-scaler (Clock divider) A division value.
N: Division factor is N+1
[7:0]
R/W
Reserved. Program to zero.