PRELIMINARY
SYSTEM CONTROLLER
S3C6400X RISC MICROPROCESSOR
3-10
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Clock generation for audio (IIS and PCM)
Figure 3-11 generates special clocks for audio interface logics, which include IIS and PCM. S3C6400X has two
IIS channels and two PCM channels, supports only two channels at any given time. Usually, EPLL generates one
special clock for an audio interface. If S3C6400X requires two independent clock frequency, i.e., there is no
integer relationship between two audio interfaces, the remaining clock can be supplied directly through external
oscillators or using MPLL.
EPLL
1
0
MUX
EPLL
MPLL
1
0
DIV
MPLL
1
0
EXTCLK
XTIpll
MUX
MPLL
CLKAUDIO0
DIV
AUDIO0
SCLK_GATE[8]
CLK_DIV2[11:8]
CLKAUDIO1
DIV
AUDIO1
SCLK_GATE[9]
CLK_DIV2[15:12]
CLK_SRC[1]
CLK_SRC[2]
CLK_DIV0[4]
1
0
2
3
4
1
0
2
3
4
MUX
AUDIO0
MUX
AUDIO1
IISCDCLK0
PCMCDCLK
IISCDCLK1
CLK_SRC[9:7]
CLK_SRC[12:10]
Figure 3-11. Audio clock generation
Clock generation for UART, SPI, and MMC
Figure 3-12 shows the clock generator for UART, SPI and MMC. There is one additional clock source, CLK27M,
to give more flexibility.
CLKUART
DIV
UART
1
0
DIV
SPI0
CLKSPI0
CLKSPI1
DIV
MMC0
CLKMMC1
DIV
MMC1
MUX
UART
MUX
MMC
2
0
1
3 2
0
1
3
2
0
1
3 2
0
1
3
CLKMMC2
2
0
1
3
EPLL
1
0
MUX
EPLL
MPLL
1
0
DIV
MPLL
1
0
EXTCLK
XTIpll
MUX
MPLL
CLK_SRC[1]
CLK_SRC[2]
CLK_DIV0[4]
MUX
SPI0,1
CLK_SRC[13]
CLK_DIV2[19:16]
CLK_SRC[15:14]
CLK_SRC[17:16]
CLK_DIV2[3:0]
CLK_DIV2[7:4]
CLK_DIV1[3:0]
CLK_DIV1[7:4]
CLK_DIV1[11:8]
CLK_SRC[19:18]
CLK_SRC[21:20]
CLK_SRC[23:22]
CLK27M
DIV
MMC2
SCLK_GATE[9]
SCLK_GATE[20]
SCLK_GATE[21]
DIV
SPI1
CLKMMC0
SCLK_GATE[24]
SCLK_GATE[25]
SCLK_GATE[26]
Figure 3-12. UART/SPI/MMC clock generation