PRELIMINARY
S3C6400X RISC MICROPROCESSOR
MULTI-FORMAT VIDEO CODEC
21-18
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Frame buffer
This section describes the memory map of the frame buffer used in FIMV-MFC V1.0 video codec module.
Y
Base Address for Y frame
Frame width in pixel unit
Stride line in pixel unit
U
Base Address for U frame
Frame width in pixel unit/2
Stride line in pixel unit/2
V
Base Address for V frame
Stride line in pixel unit/2
Frame width in pixel unit/2
Figure 21.9. Frame buffer configuration
A frame buffer is specified with the base address and the stride line. A complete image consists of Y, U, and V
component. Therefore, an image requires 3 frame buffers for Y, U, and V components. The stride line means the
width of the luminance component buffer in pixel unit and must be multiple of 8. The stride line for the U and V
frame buffers is a half of the Y frame buffer and is extracted automatically based on the stride line of the Y frame
buffer. FIMV-MFC V1.0 supports 11-bit stride line.
Figure 21.10 highlights the memory map of the frame buffer. For V frame buffer, the memory map is the same as
the U frame buffer except the base address.
FIMV-MFC V1.0 supports both little and big endian system. It means Y(0,0) in the figure 3.1 could be located in
the bit[31:24]. A user can specify the endian to the register of the host interface.