PRELIMINARY
S3C6400 RISC MICROPROCESSOR
DMA
11-7
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Peripheral-to-memory transaction under DMA controller flow control
For transactions that are not a multiple of the burst size, use both the burst and single request signals as shown in
Figure 11-2.
Peripheral
DMA
controller
DMACBREQ
DMACSREQ
DMACCLR
Figure 11-2. Peripheral-to-memory transaction comprising bursts and single requests
The two request signals are not mutually exclusive. The DMA controller monitors
DMACBREQ
, while the amount of
data left to transfer is greater than the burst size, and commences a burst transfer (from the peripheral) when
requested. When the amount of data left is less than the burst size, the DMA controller monitors
DMACSREQ
and
commences single transfers when requested
.
Memory-to- Peripheral transaction under DMA controller flow control
For transactions that are not a multiple of the burst size, use only the burst request signal as shown in Figure 11-3.
The DMAC works out the amount of data to transfer based on the transfer size.
DMA
controller
Peripheral
DMACBREQ
DMACCLR
Figure 11-3. Memory-to-Peripheral transaction comprising bursts that are not multiples of the burst size
Only
DMACBREQ
is required. The DMA controller transfers full bursts of data while the amount of data left to
transfer is greater than the burst size. When the amount of data left is less than the burst size, the DMAC again
monitors
DMACBREQ
and transfers the rest of the data when requested.
Memory-to-memory transaction under DMA controller flow control
Software programs a DMA channel memory-to-memory transfer. When it is enabled, the DMA channel commences
transfers without DMA request. It continues until one of the following occurs:
z
All the data is transferred.
z
The channel is disabled by software.
Note:
You must program memory-to-memory transfers with a low channel priority, otherwise the other DMA
channels cannot access the bus until the memory-to-memory transfer has finished, or other AHB masters
cannot perform any transaction.