Samsung S3C6400X, User Manual, Page: 1016 / 1189

PRELIMINARY
S3C6400 RISC MICROPROCESSOR UART
31-21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART FIFO STATUS REGISTER
Register Address R/W Description Reset Value
UFSTAT0 0x7F005018 R UART channel 0 FIFO status register 0x00
UFSTAT1 0x7F005418 R UART channel 1 FIFO status register 0x00
UFSTAT2 0x7F005818 R UART channel 2 FIFO status register 0x00
UFSTAT3 0x7F005C18 R UART channel 3 FIFO status register 0x00
There are three UART FIFO status registers including UFSTAT0, UFSTAT1, UFSTAT2 and UFSTAT3 in the
UART block.
UFSTATn Bit Description Initial State
Reserved [15] 0
Tx FIFO Full [14] Set to 1 automatically whenever transmit FIFO is full
during transmit operation
0 = 0-byte
≤
Tx FIFO data
≤
63-byte
1 = Full
0
Tx FIFO Count [13:8] Number of data in Tx FIFO 0
Reserved [7] 0
Rx FIFO Full [6] Set to 1 automatically whenever receive FIFO is full
during receive operation
0 = 0-byte
≤
Rx FIFO data
≤
63-byte
1 = Full
0
Rx FIFO Count [5:0] Number of data in Rx FIFO 0