PRELIMINARY
S3C6400X RISC MICROPROCESSOR
DISPLAY
CONTROLLER
14-51
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
original screen y coordinate. And the original screen y coordinate
MUST be even value.)
Window 2 Position Control B Register
Register
Address
R/W
Description
Reset
Value
VIDOSD2B
0x77100064
R/W
Video Window 2’s position control register
0x0
VIDOSD2B
Bit
Description
initial
state
OSD_RightBotX_F [21:11] Horizontal screen coordinate for right bottom pixel of OSD image
0
OSD_RightBotY_F
[10:0]
Vertical screen coordinate for right bottom pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y
coordinate MUST be odd value.)
0
Note
. Registers must have word boundary X position.
So, 24 BPP mode must have X position by 1 pixel. ( ex, X = 0,1,2,3….)
16 BPP mode must have X position by 2 pixel. ( ex, X = 0,2,4,6….)
8 BPP mode must have X position by 4 pixel. ( ex, X = 0,4,8,12….)
Window 2 Position Control C Register
Register
Address
R/W
Description
Reset
Value
VIDOSD2C
0x77100068
R/W
Video Window 2’s alpha control register
0x0
VIDOSD2C
Bit
Description
initial
state
- [24]
Reserved
0
ALPHA0_R
[23:20]
Red Alpha value(case AEN == 0)
0
ALPHA0_G
[19:16]
Green Alpha value(case AEN == 0)
0
ALPHA0_B
[15:12]
Blue Alpha value(case AEN == 0)
0
ALPHA1_R
[11:8]
Red Alpha value(case AEN == 1)
0
ALPHA1_G
[7:4]
Green Alpha value(case AEN == 1)
0
ALPHA1_B
[3:0]
Blue Alpha value(case AEN == 1)
0