PRELIMINARY
DMA
S3C6400 RISC MICROPROCESSOR
11-10
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FUNCTIONAL TIMING DIAGRAM
A peripheral asserts a DMA request and holds it active. The
DMACCLR
signal is asserted by the DMA controller
when the last data item has been transferred. When the peripheral notice that the
DMACCLR
signal has gone active
it makes the DMA request signal inactive. The DMAC controller deasserts the
DMACLR
signal when the DMA
request signal goes inactive.
HCLK/PCLK
DMACREQ
DMACCLR
HCLK/PCLK
Valid
Figure 11-6. DMA interface timing
PROGRAMMER’S MODEL
Programming the DMA controller
All transactions on the AHB Slave programming bus must be 32-bit wide. This eliminates endian issues when
programming the DMA controller.
Enabling the DMA controller
To enable the DMA controller set the DMA Enable bit in the DMACConfiguration register.
Disabling the DMA controller
To disable the DMA controller take the following steps:
1. Read the DMACEnbldChns register and ensure that all the DMA channels have been disabled. If any channels
are active refer to
Disabling a DMA channel
.
2. Disable the DMA controller by writing to the DMA Enable bit in the DMACConfiguration register.
Enabling a DMA channel
To enable the DMA channel set the Channel Enable bit in the relevant DMA channel configuration register.
Note:
The channel must be fully initialized before it is enabled. Additionally, the Enable bit of the DMA controller
must be set before any channels are enabled.