PRELIMINARY
MEMORY SUBSYSTEM
S3C6400X RISC MICROPROCESSOR
4-4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FUNCTIONAL DESCRIPTION
The Memory Subsystem can be configured by System Controller. The memory configuration register name in
System Controller is MEM_SYS_CFG. This address of this register is 0x7E00F120. System controller sends
information as follows:
z
Flash
information
NAND Flash boot enable
Advanced NAND Flash
0= Normal NAND / 1= Advanced NAND
Address
Cycle
In normal NAND, 0= 3 cycles / 1= 4 cycles
In advanced NAND, 0= 4 cycles / 1= 5 cycles
NAND Flash data bus Width
8-bit
Page Size selection
In normal NAND, 0= 256 byte / 1= 512 byte
In advanced NAND, 0= 1 kbyte / 1= 2 kbyte
z
Port
information
SROM data bus width
Can be changed by SROM Controller SFR setting.
0 : 8-bit, 1 : 16-bit
Address
Expand
0= Use Xm1DATA[31:16] as high-halfword data from memory port 1.
1= Use Xm1DATA[31:16] as high-halfword address from memory port 0.
z
Borrow address bit [26:16] for memory port 0 from data pin [31:16] of memory port 1
Boot
location
Boot location information can be checked in MEM_CFG_STAT[6:5].
CfgBootLoc[1:0]
Boot Location
2’b00
Stepping Stone area in NFCON
2’b01 SROMC
CS0
2’b10 OneNANDC
CS0
2’b11 Internal
ROM