Samsung S3C6400X, User Manual, Page: 1018 / 1189

PRELIMINARY
S3C6400 RISC MICROPROCESSOR UART
31-23
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)
There are four UART transmitting buffer registers including UTXH0, UTXH1, UTXH2 and UTXH3 in the UART
block. UTXHn has an 8-bit data for transmitting data.
UART RECIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)
There are four UART receiving buffer registers including URXH0, URXH1, URXH2 and URXH3 in the UART
block. URXHn has an 8-bit data for received data.
Register Address R/W Description Reset Value
URXH0 0x7F005024 R UART channel 0 receive buffer register 0x00
URXH1 0x7F005424 R UART channel 1 receive buffer register 0x00
URXH2 0x7F005824 R UART channel 2 receive buffer register 0x00
URXH3 0x7F005C24 R UART channel 3 receive buffer register 0x00
Note: When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an
overrun error, even though the overrun bit of UERSTATn had been cleared.
Register Address R/W Description Reset Value
UTXH0 0x7F005020 W UART channel 0 transmit buffer register -
UTXH1 0x7F005420 W UART channel 1 transmit buffer register -
UTXH2 0x7F005820 W UART channel 2 transmit buffer register -
UTXH3 0x7F005C20 W UART channel 3 transmit buffer register -
UTXHn Bit Description Initial State
TXDATAn [7:0] Transmit data for UARTn -
URXHn Bit Description Initial State
RXDATAn [7:0] Receive data for UARTn 0x00