PRELIMINARY
CAMERA INTERFACE
S3C6400X RISC MICROPROCESSOR
20-20
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
O v e r f lo w
( p r e v ie w )
IR Q _ p
IR Q _ C l_ p
O v e r f lo w
( c o d e c )
IR Q _ O v f e n
IR Q _ c
IR Q _ C l_ c
INTERRUPT
(LEVEL)
INTERRUPT
(EDGE TRIGGER)
SFR(IRQ_CLR) SET
Interrupt SET
Auto
cleared
Low to High
(cleared)
IRQ_CLR
Auto
cleared
Figure 20-17. Interrupt generation scheme
WINDOW OFFSET REGISTER 2
Register
Address
R/W
Description
Reset Value
CIWDOSFT2
0x78000014
RW
Window offset register 2
0
CIWDOFST2
Bit
Description
Initial
State
M L
Reserved
[31:27]
0
X X
WinHorOfst2
[26:16]
Window horizontal offset2 by pixel unit. (It must be 2’s multiple)
Caution :
SourceHsize-WinHorOfst- WinHorOfst2 must be 8’s
multiple and minimum 16.
0
X O
Reserved
[15:11]
0
X X
WinVerOfst2
[10:0]
Window vertical offset2 by pixel unit
0
X O