Samsung S3C6400X, User Manual, Page: 113 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER
5-7
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Memc_cmd [2:0]
Changes the state of the DRAM controller
000 = Go 001 = Sleep 010 = Wakeup 011 = Pause
100 = Configure 101~111 = Reserved
DIRECT COMMAND REGISTER
Register Address R/W Description Reset Value
P0 DIRECTCMD 0x7E000008 W 16-bit DRAM controller direct command register
P1 DIRECTCMD 0x7E001008 W 32-bit DRAM controller direct command register
PnDIRECTCMD Bit Description Initial State
[31:22] Undefined. Write as Zero
Chip number [21:20]
Bits mapped to external memory chip address bits.
Memory
command
[19:18]
Determine the command required
00 = Prechargeall
01 = Autorefresh
10 = MRS or EMRS
11 = NOP
Bank address [17:16]
Bits mapped to external memory bank address bits when
command is MRS or EMRS access.
[15:14] Undefined. Write as Zero
Address_13_to_
0
[13:0]
Bits mapped to external memory address bits [13:0] when
command is MRS or EMRS access.
MEMORY CONFIGURATION REGISTER
Register Address R/W Description Reset Value
P0MEMCFG 0x7E00000C R/W 16-bit DRAM controller memory config register 0x01_0020
P1MEMCFG 0x7E00100C R/W 32-bit DRAM controller memory config register 0x01_0020
PnMEMCFG Bit Description Initial
State
cke_config [31]
Select CKE control configuration. P1MEMCFG only.
0 = Supports one CKE control.
1 = Supports individual CKE control.
0
Reserved [30:23] Read undefined. Write as zero.