PRELIMINARY
S3C6400X RISC MICROPROCESSOR
POST
PROCESSOR
15-3
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
A Source and Destination Image Data Format
In FIMV POST Processor, two output modes such as DMA mode and FIFO mode are available as shown in the
following Figure 15-2.
In FIFO mode (if LCDPathEnable = 1, For more information refer to chapter 6. Register File List), destination
image is transferred to the FIFO in display controller (or some other IP with FIFO interface) without additional
memory bandwidth such as POST-to-Memory and Memory-to-Display Controller. The source image format and
the destination image format
is
described in
Chapter 2.2 FIFO mode
.
Figure 15-2. Two input and output modes in POST Processor Block Diagram