Samsung S3C6400X, User Manual, Page: 401 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR DISPLAY CONTROLLER
14-39
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
edge
IHSYNC [6] This bit indicates the HSYNC pulse polarity.
0 = normal 1 = inverted 0
IVSYNC [5] This bit indicates the VSYNC pulse polarity.
0 = normal 1 = inverted 0
IVDEN [4] This bit indicates the VDEN signal polarity.
0 = normal 1 = inverted 0
Reserved [3:0] 0x0
VIDEO Time Control 0 Register
Register Address R/W Description Reset Value
VIDTCON0 0x77100010 R/W Video time control 0 register 0x0000_0000
VIDTCON0 Bit Description Initial State
VBPDE [31:24] Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period. (Only for the even field
of YVU interface) 0x0
VBPD [23:16] Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period. 0x0
VFPD [15:8] Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period. 0x0
VSPW [7:0] Vertical sync pulse width determines the VSYNC pulse's high level
width by counting the number of inactive lines. 0x0
Video Time Control 1 Register
Register Address R/W Description Reset Value
VIDTCON1 0x77100014 R/W Video time control 1 register 0x0000_0000
VIDTCON1 Bit Description Initial state
VFPDE [31:24] Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period. (Only for the even field
of YVU interface) 0x0
HBPD [23:16] Horizontal back porch is the number of VCLK periods between the
falling edge of HSYNC and the start of active data. 0x0
HFPD [15:8] Horizontal front porch is the number of VCLK periods between the
end of active data and the rising edge of HSYNC. 0x0
HSPW [7:0] Horizontal sync pulse width determines the HSYNC pulse's high
level width by counting the number of the VCLK. 0x0