Samsung S3C6400X, User Manual, Page: 212 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR CF CONTROLLER
9-25
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ATA_CFG
Register Address Description Reset Value
ATA_CFG 0x70301918 ATA configuration for ATA interface 0x0000_0000
ATA_CFG Bits Description R/W Reset
Value
Reserved [31:10] Reserved bits R 0x0
UDMA_AUTO_M
ODE [9] Determines whether to continue automatically in case of early
termination in UDMA mode by Device. This bit must not be
changed during runtime operation.
0: stay in pause state and wait for CPU’s action.
1: continue automatically
R/W 0x0
SBUF_EMPTY_M
ODE [8] Determines whether to continue automatically when source
buffer is empty. This bit must not be changed during runtime
operation.
0: continue automatically with new source buffer address.
1: stay in pause state and wait for CPU’s action.
** With the SBUF_EMPTY_MODE is "0" and the transmission
data size is bigger than the source buffer size, the source
buffer empty interrupt (SBUF_EMPTY_INT) happens before
setting of the second source buffer base address and size.
Then ATA host controller brings data from the first source
buffer repeatedly. To avoid this, after 1st source buffer is
empty, the “SBUF_EMPTY_MODE” bit automatically changes
to HIGH even though the default is “0”. Therefore you must
issue “CONTINUE” command. If you don’t want CPU to
interfere, change the next source buffer address to”0” at the
bit 8 before/after the next base address and size.
R/W 0x0
TBUF_FULL_MO
DE [7] Determines whether to continue automatically when track
buffer is full. This bit must not be changed during runtime
operation.
0: continue automatically with new track buffer address.
1: stay in pause state and wait for CPU’s action.
** With the TBUF_FULL_MODE is "0" and the transmission
data size is bigger than the target buffer size, the target buffer
full interrupt(TBUF_FULL_INT) happens before setting of the
second target buffer base address and size. Then ATA host
controller sends data to the first target buffer repeatedly. To
avoid this, after 1st target buffer is full, the
“TBUF_FULL_MODE” bit automatically changes to HIGH
even though the default is “0”. Therefore you must issue
“CONTINUE” command. If you don’t want CPU to interfere,
change the next source buffer address to”0” at the bit 8
before/after the next base address and size.
R/W 0x0