PRELIMINARY
S3C6400X RISC MICROPROCESSOR
ELECTRICAL DATA
41-37
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
I2SLRCLK(Output)
I2SSCLK(Output)
I2SSDO(Output)
T
LRId
T
DS
T
DH
Figure 41-24. IIS Interface Timing (Master / TX)
Table 41-15. IIS Controller Module Signal Timing Constants(I2S Master / TX)
(VDDINT= 1.0V
±
0.05V, TA = -40 to 85
°
C, VDDPCM = 3.3V
±
0.3V, 2.5V
±
0.25V, 1.8V
±
0.15V)
Parameter Symbol
Min.
Typ.
Max
Unit
LR Clock Input Delay
TLRId 5
-
ns
Serial Data Setup Time
TDS 10 -
ns
Serial Data Hold Time
TDH 10 -
ns