Samsung S3C6400X, User Manual, Page: 112 / 1189

PRELIMINARY
DRAM CONTROLLER S3C6400X RISC MICROPROCESSOR
5-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
REGISTER DESCRIPTION
DRAM CONTROLLER STATUS REGISTER
Register Address R/W Description Reset Value
P0MEMSTAT 0x7E000000 R 16-bit DRAM controller status register 0xAB0
P1MEMSTAT 0x7E001000 R 32-bit DRAM controller status register 0xAB4
PnMEMSTAT Bit Description Initial State
Reserved [31:14] Read undefined.
Memory banks [13:12]
The maximum number of banks that DRAM controller supports on
each chip.
00 = 4 banks
00
Exclusive
monitors
[11:10]
The number of exclusive access monitor resources
10 = 2 monitors
10
Reserved [9] Read always zero. 0
Memory chips [8:7]
The maximum number of different chip selects that DRAM
controller can supports:
11 = 4 chips
However, S3C6400X uses only two chip select signals per DRAM
controller.
11
Memory type [6:4]
The type of SDRAM that DRAM controller supports:
100 = Support SDR SDRAM (normal or mobile) and DDR SDRAM
(normal or mobile)
100
Memory width [3:2]
The width of the external memory
00 = 16-bit 01 = 32-bit 10 = 64-bit 11 = reserved
00 / 01
Controller status [1:0]
The status of the DRAM controller
00 = Config. 01 = Ready 10 = Paused 11 = Low-Power
00
DRAM CONTROLLER COMMAND REGISTER
Register Address R/W Description Reset Value
P0MEMCCMD 0x7E000004 W 16-bit DRAM controller command register
P1MEMCCMD 0x7E001004 W 32-bit DRAM controller command register
PnMEMCCMD Bit Description Initial State
[31:3] Undefined. Write as Zero