PRELIMINARY
S3C6400X RISC MICROPROCESSOR
POST
PROCESSOR
15-31
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Next Frame DMA End Address Register for Output Cb and Cr
Register
Address
R/W
Bit
Description
Reset Value
NxtADDREnd_oCb 0x77000094 R/W [30:0]
Next Frame DMA (Buffer 1) End
address for destination Cb component
(For more information refer to chapter
15-4)
0x20006300
Register
Address
R/W
Bit
Description
Reset Value
NxtADDREnd_oCr 0x77000098 R/W [30:0]
Next Frame DMA (Buffer 1) End
address for destination Cr component
(For more information refer to chapter
15-4)
0x20006300
POSTENVID Register for Enable Video Processing
Register
Address
R/W
Bit
Description
Reset Value
POSTENVID 0x7700009C
R/W [31]
Enable Video Processing. It enables the operation of
POST Processor. It is de-asserted automatically
after operation of the current frame is finished. It
must be disabled (POSTENVID=0) during control
register configuration state. It can not be de-asserted
during operation. But it can be de-asserted in case
that POST Processor is only ready for operation.
0x0