PRELIMINARY
S3C6400X RISC MICROPROCESSOR
DISPLAY
CONTROLLER
14-65
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
010 = 19 bit ( A:6:6:6 )
011 = 18 bit ( A:6:6:5 )
100 = 18 bit ( 6:6:6 )
101 = 16 bit ( A:5:5:5 )
110 = 16 bit ( 5:6:5 )
I80 / RGB Trigger Control Register
Register
Address
R/W
Description
Reset Value
TRIGCON 0x771001A
4
R/W
I80 / RGB Trigger Control Register
0x0
TRIGCON
Bit
Description
Initial State
reserved [7:3]
Must be ‘0’
0
SWFRSTATUS
[2]
Frame Done Status [Read Only]
0 : Indicate I80 frame transfer is not finished
1 : Indicate I80 frame transfer finished
* Clear Condition: Read or New Frame Start
* Only when TRGMODE is ‘1’
0
SWTRGCMD
[1]
1 : Software Triggering Command [Write Only]
* Only when TRGMODE is ‘1’
0
TRGMODE [0]
Software Trigger enable control
0 : Disable
1 : Enable
0
LCD I80 Interface Control 0
Register
Address
R/W
Description
Reset Value
I80IFCONA0 0x771001B0
R/W
I80
Interface control for Main LDI(LCD)
0x0
I80IFCONA1 0x771001B4
R/W
I80
Interface control for Sub LDI(LCD)
0x0
I80IFCONAx
Bit
Description
Initial State
- [22:20]
Reserved
0
LCD_CS_SETUP [19:16]
Numbers of clock cycles for the active period of the address
signal enable to the chip select enable.
0
LCD_WR _SETUP
[15:12]
Numbers of clock cycles for the active period of the CS
signal enable to the write signal enable.
0