Samsung S3C6400X, User Manual, Page: 119 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR DRAM CONTROLLER
5-13
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
T_XP REGISTER
Register Address R/W Description Reset Value
P0T_XP 0x7E000040 R/W 16-bit DRAM controller t_XP register 0x01
P1T_XP 0x7E001040 R/W 32-bit DRAM controller t_XP register 0x01
PnT_XP Bit Description Initial State
[31:8] Read undefined. Write as Zero
t_XP [7:0] Set the exit power down command time in memory clock cycles. 0x01
T_XSR REGISTER
Register Address R/W Description Reset Value
P0T_XSR 0x7E000044 R/W 16-bit DRAM controller t_XSR register 0x0A
P1T_XSR 0x7E001044 R/W 32-bit DRAM controller t_XSR register 0x0A
PnT_XSR Bit Description Initial State
[31:8] Read undefined. Write as Zero
t_XSR [7:0] Set the exit self refresh command time in memory clock cycles. 0x0A
T_ESR REGISTER
Register Address R/W Description Reset Value
P0T_ESR 0x7E000048 R/W 16-bit DRAM controller t_ESR register 0x14
P1T_ESR 0x7E001048 R/W 32-bit DRAM controller t_ESR register 0x14
PnT_ESR Bit Description Initial State
[31:8] Read undefined. Write as Zero
t_ESR [7:0] Set the self refresh command time in memory clock cycles. 0x14
MEMORY CONFIGURATION 2 REGISTER
Register Address R/W Description Reset Value
P0MEMCFG2 0x7E00004C R/W 16-bit DRAM controller configuration register 0x0B00
P1MEMCFG2 0x7E00104C R/W 32-bit DRAM controller configuration register 0x0B40
PnMEMCFG2 Bit Description Initial State
Reserved [31:13] Read undefined. Write as Zero.