Samsung S3C6400X, User Manual, Page: 863 / 1189

PRELIMINARY
USB2.0 HS OTG S3C6400X RISC MICROPROCESSOR
26-56
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
value equals :
Vbus pulse time in PHY clocks /1,024
DEVICE LOGICAL ENDPOINT-SPECIFIC REGISTERS
A logical endpoint is unidirectional: it can be either IN or OUT. To represent a bidirectional endpoint, two logical
endpoints are required, one for the IN direction and the other for the OUT direction. This is also true for control
endpoints. The registers and register fields described in this section may pertain to IN or OUT endpoints, or both,
or specific endpoint types are noted.
DEVICE CONTROL IN ENDPOINT 0 CONTROL REGISTER (DIEPCTL0)
This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for
endpoints 1-15.
Register Address R/W Description Reset Value
DIEPCTL0 0x7C00_0900 R/W Device Control IN Endpoint 0 Control Register 32 bits
DIEPCTL0 Bit R/W Description Initial State
EPEna [31] R_WS_
SC
Endpoint Enable
Indicates that data is ready to be transmitted on the
endpoint. The core clears this bit before setting any
of the following interrupts on this endpoint.
·
Endpoint Disabled
· Transfer Completed
1’b0
EPDis [30] R_WS_
SC
Endpoint Disable
The application sets this bit to stop transmitting data
on an endpoint, even before the transfer for that
endpoint is complete. The application must wait for
the Endpoint Disabled interrupt before treating the
endpoint as disabled. The core clears this bit before
setting the Endpoint Disabled Interrupt. The
application must set this bit only if Endpoint Enable
is already set for this endpoint. 1’b0
[29:28] Reserved 2’b0
SetNAK [27] WO Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the
transmission of NAK handshakes on an endpoint.
The core can also set this bit for an endpoint after a
SETUP packet is received on that endpoint. 1’b0
CNAK [26] WO Clear NAK
A write to this bit clears the NAK bit for the endpoint. 1’b0
TxFNum [25:22] RO TxFIFO Number
This value is always set to 0, indicating that control
IN endpoint 0 data is always written in the Non- 4’h0