PRELIMINARY
S3C6400X RISC MICROPROCESSOR
ONENAND CONTROLLER
7-1
7
ONENAND CONTROLLER
This chapter describes the functions and usage of OneNAND controller in S3C6400X RSIC microprocessor.
OVERVIEW
S3C6400X supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory
via shared memory port 0. It supports maximum 2 banks by using two controllers. The OneNAND Controller is
an
Advanced Microcontroller Bus Architecture
(AMBA 2) compliant System-on-Chip peripheral. The OneNAND
Controller provides simultaneous support for maximum two memory banks. Each memory bank supports only
Muxed OneNAND. To use OneNAND Flash instead of NAND Flash, ‘XSELNAND’ pin must be connected to
zero (Low).
FEATURE
The OneNAND controller includes the following:
z
Supports maximum 2 banks by using two OneNAND Controllers
z
Supports asynchronous/synchronous muxed OneNAND memory
z
Supports 16-bit wide external memory data paths
z
Supports SINGLE/INCR4/INCR8 burst transfers for 32-bit AHB data bus
z
Supports SINGLE Word transfers for 32-bit AHB SFR bus
z
Supports only ERROR/OKAY response for both AHB buses
z
Data buffering in order to achieve maximum performance
z
Asynchronous FIFOs between the flash controller core and the bus system interface for speed
matching
z
Supports Erase commands through address mapping
z
Supports Copy modes as register commands
z
Supports write-synchronous mode if OneNAND device ID is 0x0040, 0x0048, and 0x0058.
z
Supports write-synchronous mode if OneNAND device ID is 0x0030, 0x0034 and OneNAND
version ID bit [9:8] is not 2’b00.
z
Supports up to LDM4/STM4 when map 01 page-access command is used.
If the device density
is 128Mb or 256Mb, no more than 1-word access is recommended for 01 page-access
command
.