PRELIMINARY
S3C6400 RISC MICROPROCESSOR
DMA
11-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Signal timing
The timing behavior of the DMA signals is described below:
DMA request signal DMAC{L}(B/S)REQx
Notifies the DMA controller about the peripheral which is ready to proceed with a DMA transfer of
the indicated size.
Active HIGH. Sampled by the DMA controller on the positive edge of
HCLK
.The DMA request
signals are used in conjunction with the
DMACCLR
signal to perform handshaking.
DMA Acknowledge or Clear DMACCLRx
Indicates to the slave that a DMA transfer is completed.
Active HIGH.
DMA Terminal Count DMACTCx
Indicates to the slave that the end of packet has been reached.
Active HIGH.
Note:
If the DMA request source does not use the same clock as the DMA controller, then the request must be
synchronized by setting the relevant bit in the DMACSync register.