PRELIMINARY
VECTORED INTERRUPT CONTROLLER
S3C6400X RISC MICROPROCESSOR
12-10
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 = FIQ interrupt
There is one bit of the register for each interrupt source.
Interrupt Enable Register, VICINTENABLE
Bits
Name
Type
Function
[31:0] IntEnable RW
Enables the interrupt request lines, which allow the
interrupts to reach the processor.
Read:
0 = interrupt disabled (reset)
1 = Interrupt enabled
The interrupt enable can only be set using this register.
The VICINTENCLEAR Register must be used to disable
the interrupt enable.
Write:
0 = no effect
1 = interrupt enabled.
On reset, all interrupts are disabled.
There is one bit of the register for each interrupt source.
Interrupt Enable Clear, VICINTENCLEAR
Bits
Name
Type
Function
[31:0] IntEnable
Clear W Clears corresponding bits in the VICINTENABLE Register:
0 = no effect
1 = interrupt disabled in VICINTENABLE Register.
There is one bit of the register for each interrupt source.
Software Interrupt Register, VICSOFTINT
Bits Name
Type
Function
[31:0] SoftInt RW
Setting a bit HIGH generates a software interrupt for the
selected source before interrupt masking.