PRELIMINARY
HOST INTERFACE
S3C6400X
RISC MICROPROCESSOR
24-16
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Control Register (CTRL)
BSEL[3:0] = 0000, MP_A[1:0] = 00, R/W, Reset value = 0x0000
Field
Bit
Description
Initial State
Reserved [15:13]
00
BLEN[8:0] [12:4]
Burst
length for transfer
The basic unit is a 32-bit word. Maximum burst length is 256
words.
0 = No transaction
1 = Single Write or Single Read
N = N-word
* Note that BLEN must be 0 not to issue a new CPUIF
command.
0_0000_0000
REP_WRITE
[3]
Repeated Burst Write Enable
0 = No ‘Repeated Burst Write’
1 = If set, “Burst Write” is treated as “Repeated Burst Write”
0
CPUIF_RESET
[2]
Reset of the CPUIF Client
0 = This bit is used a soft reset signal of the CPUIF Client.
1 = Therefore, this bit must be de-asserted by software.
0
Reserved
[1]
This field must be fixed to ‘0’
0
READ_WRITE [0]
Read
or
Write
0 = Write operation, 1 = Read operation
0
Interrupt Enable Register (INTE)
BSEL[3:0] = 0000, MP_A[1:0] = 01, R/W, Reset value = 0x2000
Field
Bit
Description
Initial State
WFIFO_THRES [15:8]
Threshold
of the empty elements in WFIFO
This value specifies the threshold of the partial emptiness. For
example, if WFIFO_THRES is 8, STAT[7] becomes 1 when 16
and more elements in WFIFO are empty.
0x20
WFIFO_PEMPTY
[7]
WFIFO partial empty interrupt enable
Interrupt occurs (i.e., INTR becomes 1) when INTE [7] = 1 and
STAT [7] = 1.
0
Reserved [6:2]
-
0
WFIFO
[1]
WFIFO interrupt enable
Interrupt occurs when INTE [1] = 1 and STAT [1] = 1.
0
RFIFO
[0]
RFIFO interrupt enable
Interrupt occurs when INTE [0] = 1 and STAT [0] = 1.
0