Samsung S3C6400X, User Manual, Page: 485 / 1189

PRELIMINARY
TV SCALER S3C6400X RISC MICROPROCESSOR
16-18
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MODE Control Register
Register Address R/W Description Reset Value
MODE 0x76300000 R/W Mode Register [31:0] 0x00070B12
MODE Bit Description Initial State
ExtFIFOIn [31] In FIFO Mode Enable. 1 for FIFO mode and 0 for DMA mode 0
CLKVALUP [30] Select CLKVAL_F update timing control
0 = always
1 = start of a frame (only once per frame)
0
CLKVAL_F [29:24] Determine the rates of TSCLK and CLKVAL[5:0]
TSCLK = Clock source / (1) where CLKVAL >= 1
Note. The maximum frequency of VCLK is 66MHz.
0
CLKDIR [23] Select the clock source as direct or divide using CLKVAL_F
register
0 = Direct clock (frequency of TSCLK = frequency of Clock source)
1 = Divided by CLKVAL_F
0
CLKSEL_F [22:21] Select the Video Clock source
00 = HCLK
01 = PLL Ext Clock input
10 = reserved
11 = 27MHz Ext Clock input
0
OutYCbCrFormat [20:19] It determines the byte organization of word data when the
destination image is interleaved YCbCr format. For more
information refer to Fig.16-2(b) .
0
OutRGB [18] It indicates the output color space of destination image. 0 for
YCbCr or 1 for RGB.
1
DST420 [17] 0 for YCbCr422 and 1 for YCbCr420 destination format. It is valid
only for YCbCr destination image (i.e. OutRGB = 0)
1
R2YSel [16] Select color space conversion equation from RGB to YCbCr. 1 for
YCbCr Wide range and 0 for YCbCr Narrow range.
1
InYCbCrFormat_
MSB
[15] It determines the MSB of byte organization of word data when the
source image is interleaved YCbCr format. For more information
refer to Fig.16-2(b).
0