PRELIMINARY
S3C6400
RISC MICROPROCESSOR
PRODUCT OVERVIEW
1-23
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
RESET O
Memory port 0 CF CARD Reset
INPACK I
Memory port 0 CF Input acknowledge in I/O mode
REG O
Memory port 0 CF Interrupt request from CF card
WEn O
Memory port 0 CF Write enable strobe
OEn O
Memory port 0 CF Output enable strobe
CDn I
Memory port 0 CF Card detection
DQM[1:0]
O
Memory port 0 DRAM Data Mask
RAS O
Memory port 0 DRAM Row Address Strobe
CAS O
Memory port 0 DRAM Column Address Strobe
SCLK O
Memory port 0 DRAM Clock
SCLKn O
Memory port 0 DRAM Inverted Clock of Xm0SCLK
SCKE
O
Memory port 0 DRAM Clock Enable
DQS[1:0]
IO
Memory port 0 DRAM Data Strobe
WEn O
Memory port 0 DRAM Write Enable
AP O
Memory port 0 DRAM Auto Precharge
•
DRAM(mDDR and mSDRAM) Memory Port
•
Shared Memory Port (SROMC / DRAM1)
I/O
Function
Signal
0
1
0
1
Xm1CKE
O
Xm1CKE
Xm1SCLK
IO
Xm1SCLK
Xm1SCLKn
O
Xm1SCLKn
Xm1CSn[1:0]
O
Xm1CSN[1:0]
Xm1ADDR[15:0]
O
Xm1ADDR[15:0]
Xm1RASn
O
Xm1RAS
Xm1CASn
O
Xm1CAS
Xm1WEn
O
Xm1WEN
Xm1DATA[15:0]
IO
Xm1DATA[15:0]
Xm1DATA[31:16]
IO O
Xm1DATA[31:16] Xm0ADDR[26:16]
Xm1DQM[3:0]
O
Xm1DQM[3:0]
Xm1DQS[3:0]
IO
Xm1DQS[3:0]