PRELIMINARY
DMA
S3C6400 RISC MICROPROCESSOR
11-22
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Channel linked list item register, DMACCxLLI
The eight read/write DMACCxLLI registers contain a word aligned address of the next
Linked List Item
(LLI). If the
LLI is, then the current LLI is the last in the chain, and the DMA channel is disabled once all DMA transfers
associated with it are completed.
Note:
Programming this register when the DMA channel is enabled has unpredictable side effects.
To make loading LLIs more efficient for some systems, the LLI data structures can be made 4-word aligned.
Table 11-18 shows the bit assignment of a DMACCxLLI register.
Table 11-18. Bit Assignment of DMACCxLLI register
DMACCxLLI
Bits
Type
Function
LLI
[31:2]
R/W
Linked list item. Bits [31:2] of the address for the next LLI. Address
bits [1:0] are.
R
[1]
R/W
Reserved, and must be written as 0,masked on read.
LM
[0]
R/W
AHB master select for loading the next LLI:
LM = 0 = AHB master 1
LM = 1 = AHB master 2.
Channel control register, DMACCxControl0
The eight read/write DMACCxControl0 registers contain DMA channel control information such as the burst size,
and transfer width.
Each register is programmed directly by software before the DMA channel is enabled. When the channel is enabled
the register is updated by following the linked list when a complete packet of data has been transferred.
Reading the register whilst the channel is active does not give useful information. This is because by the time that
software has processed the value read, the channel might have progressed. It is intended to be read only when a
channel has stopped.
Table 11-19 shows the bit assignment of a DMACCxControl0 register.
Table 11-19. Bit Assignment of DMACCxControl0 register
DMACCxControl
Bits
Type
Function
I
[31]
R/W
Terminal count interrupt enable bit. It controls whether the current LLI is
expected to trigger the terminal count interrupt.
Prot
[30:28]
R/W
Protection.
DI
[27]
R/W
Destination increment. When set the destination address is incremented
after each transfer.
SI
[26]
R/W
Source increment. When set the source address is incremented after
each transfer.
D
[25]
R/W
Destination AHB master select:
0 = AHB master 1 (AXI_SPINE) selected for the destination transfer.
1 = AHB master 2 (AXI_PERI) selected for the destination transfer.