PRELIMINARY
PCM AUDIO INTERFACE
S3C6400X RISC MICROPROCESSOR
37-18
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PCM
FIFO
STATUS
REGISTER
The PCM_FIFO_STAT register is used to report FIFO status.
Register
Address
R/W
Description
Reset Value
PCM_FIFO_STAT 0x7F009018
0x7F00A018
R
PCM FIFO Status
0x00000000
The bit definitions for the PCM_IRQ_STATUS Register are described below:
PCM_FIFO_STAT
Bit
Description
Initial State
Reserved [31:20]
Reserved
TXFIFO_COUNT
[19:14] To indicate TXFIFO usage.
0
TXFIFO_EMPTY [13]
To
indicate whether TXFIFO is empty.
0
TXFIFO_ALMOST_EMPTY [12]
To
indicate
whether TXFIFO is almost empty.
0
TXFIFO_FULL
[11]
To indicate whether TXFIFO is full.
0
TXFIFO_ALMOST_FULL [10]
To
indicate
whether TXFIFO is almost full.
0
RXFIFO_COUNT
[9:4]
To indicate RXFIFO usage.
RXFIFO_EMPTY
[3]
To indicate whether RXFIFO is empty.
0
RXFIFO_ALMOST_EMPTY
[2]
To indicate whether RXFIFO is almost empty.
0
RX_FIFO_FULL
[1]
To indicate whether RXFIFO is full.
0
RX_FIFO_ALMOST_FULL [0]
To
indicate
whether RXFIFO is almost full.
0
PCM
INTERRUPT
CLEAR
REGISTER
The PCM_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing
interrupt asserted. Writing any values on this register clears interrupts for ARM. Reading this register is not
allowed. Clearing interrupt must be prior to resolving the interrupt condition; otherwise another interrupt that would
occur after this interrupt may be ignored.
Register
Address
R/W
Description
Reset Value
PCM_CLRINT 0x7F009020
0x7F00A020
W
PCM INTERRUPT CLEAR
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