Samsung S3C6400X, User Manual, Page: 852 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR USB2.0 HS OTG
26-45
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
WC This is generated only in Internal DMA mode when
there is an AHB error during AHB read/write. The
application can read the corresponding channel’s
DMA address register to get the error address.
ChHltd [1] R_SS_
WC
Channel Halted
Indicates the transfer completed abnormally either
because of any USB transaction error or in response
to disable request by the application. 1’b0
XferCompl [0] R_SS_
WC
Transfer Completed
Transfer completed normally without any errors. 1’b0
HOST CHANNEL-n INTERRUPT MASK REGISTER (HCINTMSKn)
Channel_number : 0
≤
n
≤
15
This register reflects the mask for each channel status described in the previous section.
·
Mask interrupt : 1’b0
·
Unmask interrupt : 1’b1
Register Address R/W Description Reset Value
HCINTMSKn 0x7C00_050
C+n*20h
R/W Host Channel-n interrupt Mask Register 32 bits
HCINTMSKn Bit R/W Description Initial State
[31:11] Reserved 21’h0
DataTglErrMsk [10] R_W Data Toggle Error Mask 1’b0
FrmOvrunMsk [9] R_W Frame Overrun Mask 1’b0
BblErrMsk [8] R_W Babble Error Mask 1’b0
XactErrMsk [7] R_W Transaction Error Mask 1’b0
NyetMsk [6] R_W NYET Response Received Interrupt Mask 1’b0
AckMsk [5] R_W ACK Response Received Interrupt Mask 1’b0
NakMsk [4] R_W NAK Response Received Interrupt Mask 1’b0
StallMsk [3] R_W STALL Response Received Interrupt Mask 1’b0
AHBErrMsk [2] R_W AHB Error Mask 1’b0
ChHltdMsk [1] R_W Channel Halted Mask 1’b0
XferComplMsk [0] R_W Transfer Completed Mask 1’b0
HOST CHANNEL-n TRANSFER SIZE REGISTER (HCTSIZn)
Channel_number : 0
≤
n
≤
15
Register Address R/W Description Reset Value
HCTSIZn 0x7C00_0510
+n*20h
R/W Host Channel-n Transfer Size Register 32 bits