Samsung S3C6400X, User Manual, Page: 1044 / 1189

PRELIMINARY
S3C6400
RISC MICROPROCESSOR Pulse Width Modulation Timer
32-21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
TCNTB4 (TIMER4 COUNTER REGISTER)
Register Offset R/W Description Reset Value
TCNTB4
0x7F00603c R/W
Timer 4 Count Buffer Register
0x0000_0000
TCNTB4 Bit R/W Description Initial State
Timer 4 Count Buffer [31:0] R/W Timer 4 Count Buffer Register 0x00000000
TCNTO4 (TIMER4 OBSERVATION REGISTER)
Register Offset R/W Description Reset Value
TCNTO4
0x7F006040 R
Timer 4 Count Observation Register
0x0000_0000
TCNTO4 Bit R/W Description Initial State
Timer 4 Count Observation [31:0] R Timer 4 Count Observation Register 0x00000000
TINT_CSTAT(INTERRUPT CONTROL AND STATUS REGISTER)
Register Offset R/W Description Reset Value
TINT_CSTAT
0x7F006044 R/W
Timer Interrupt Control and Status Register
0x0000_0000
TINT_CSTAT Bit R/W Description Initial State
Reserved [31:10] R Reserved Bits 0x00000
Timer 4 Interrupt Status [9] R/W Timer 4 Interrupt Status Bit. Clears by writing ‘1’
on this bit. 0x0
Timer 3 Interrupt Status [8] R/W Timer 3 Interrupt Status Bit. Clears by writing ‘1’
on this bit. 0x0
Timer 2 Interrupt Status [7] R/W Timer 2 Interrupt Status Bit. Clears by writing ‘1’
on this bit. 0x0
Timer 1 Interrupt Status [6] R/W Timer 1 Interrupt Status Bit. Clears by writing `1’
on this bit. 0x0
Timer 0 Interrupt Status [5] R/W Timer 0 Interrupt Status Bit. Clears by writing ‘1’
on this bit. 0x0
Timer 4 interrupt Enable [4] R/W Timer 4 Interrupt Enable.
1 – Enabled 0 – Disabled 0x0
Timer 3 interrupt Enable [3] R/W Timer 3 Interrupt Enable.
1 – Enabled 0 – Disabled 0x0