PRELIMINARY
SYSTEM CONTROLLER
S3C6400X RISC MICROPROCESSOR
3-22
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
NOTE1:
The output frequency is calculated by using the following equation:
F
OUT
= MDIV X F
IN
/ (PDIV X 2
SDIV
)
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
MDIV:
64
≤
MDIV
≤
1023
PDIV:
1
≤
PDIV
≤
63
SDIV:
0
≤
SDIV
≤
5
F
VCO
(=MDIV X F
IN
/ PDIV): 750MHz
≤
F
VCO
≤
1400MHz
F
OUT
: 24MHz
≤
F
OUT
≤
1400MHz
F
IN
: 10Mhz
≤
F
IN
≤
20Mhz
FIN
(MHz)
Target
FOUT
(MHz)
MDIV PDIV SDIV
12 266 532 6
2
12 400 400 6
1
12 533 533 6
1
12 667 667 6
1
EPLL_CON0
BIT
DESCRIPTION
RESET VALUE
ENABLE
[31]
PLL enable control (0: disable, 1: enable)
0
RESERVED [30:24]
RESERVED
0x00
MDIV
[23:16]
PLL M divide value
0x20
RESERVED [15:14]
RESERVED
0x0
PDIV
[13:8]
PLL P divide value
0x1
RESERVED [7:3]
RESERVED 0x00
SDIV
[2:0]
PLL S divide value
0x2
EPLL_CON1
BIT
DESCRIPTION
RESET VALUE
RESERVED [30:16]
RESERVED
0x0000
KDIV
[15:0]
PLL K divide value
0x9111
The reset value of EPLL_CON0 / EPLL_CON1 generate 97.70MHz output clock respectively, if the input clock
frequency is 12MHz.