PRELIMINARY
USB2.0 HS OTG
S3C6400X RISC MICROPROCESSOR
26-44
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
transaction.
·
2’b00 : Mid. This is the middle payload of this
transaction.
·
2’b01 : End. This is the last payload of this
transaction.
HubAddr
[13:7]
R_W
Hub Address
This field holds the device address of the transaction
translator’s hub.
7’h0
PrtAddr
[6:0]
R_W
Port Address
This field is the port number of the recipient
transaction translator.
7’h0
HOST CHANNEL-n INTERRUPT REGISTER (HCINTn)
Channel_number : 0
≤
n
≤
15
This register indicates the status of a channel with respect to USB- and AHB-related events. The application must
read this register when the Host Channels Interrupt bit of the Core Interrupt register is set. Before the application
can read this register, it must first read the Host All Channels Interrupt register to get the exact channel number
for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the HAINT and GINTSTS registers.
Register
Address
R/W
Description
Reset Value
HCINTn 0x7C00_0508
+n*20h
R/W
Host Channel-n interrupt Register
32 bits
HCINTn
Bit
R/W
Description
Initial State
[31:11]
Reserved
21’h0
DataTglErr [10]
R_SS_
WC
Data Toggle Error
1’b0
FrmOvrun [9]
R_SS_
WC
Frame Overrun
1’b0
BblErr [8]
R_SS_
WC
Babble Error
1’b0
XactErr [7]
R_SS_
WC
Transaction Error
1’b0
NYET [6]
R_SS_
WC
NYET Response Received Interrupt
1’b0
ACK [5]
R_SS_
WC
ACK Response Received Interrupt
1’b0
NAK [4]
R_SS_
WC
NAK Response Received Interrupt
1’b0
STALL [3]
R_SS_
WC
STALL Response Received Interrupt
1’b0
AHBErr
[2]
R_SS_ AHB Error
1’b0