Samsung S3C6400X, User Manual, Page: 977 / 1189

PRELIMINARY
SPI CONTROLLER S3C6400X RISC MICROPROCESSOR
29-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
0: Disable 1:Enable
IntEnTxOverrun [3]
R/W
Interrupt Enable for TxOverrun
0: Disable 1:Enable
1’b0
IntEnTxUnderrun [2]
R/W
Interrupt Enable for TxUnderrun. In slave
mode, this bit must be clear first after turning
on slave TX path.
0: Disable 1:Enable
1’b0
IntEnRxFifoRdy [1]
R/W
Interrupt Enable for RxFifoRdy(INT mode)
0: Disable 1:Enable
1’b0
IntEnTxFifoRdy [0]
R/W
Interrupt Enable for TxFifoRdy(INT mode)
0: Disable 1:Enable
1’b0
Register Address R/W Description Reset Value
SPI_STATUS(Ch0) 0x7F00B014 R SPI status register 0x0
SPI_STATUS(Ch1) 0x7F00C014 R SPI status register 0x0
SPI_STATUS Bit Description Initial State
TX_done [21] R
Indication of transfer done in Shift register
0 : all case except blow case
1 : when tx fifo and shift register are empty
1’b0
Trailing_byte [20] R Indication that trailing count is zero 1’b0
RxFifoLvl [19:13]
R
Data level in RX FIFO
0 ~ 7’h40 byte
7’b0
TxFifoLvl [12:6]
R
Data level in TX FIFO
0 ~ 7’h40 byte
7’b0
RxOverrun [5]
R
Rx Fifo overrun error
0: no error, 1: overrun error
1’b0
RxUnderrun [4]
R
Rx Fifo underrun error
0: no error, 1: underrun error
1’b0
TxOverrun [3]
R
Tx Fifo overrun error
0: no error, 1: overrun error
1’b0
TxUnderrun [2]
R Tx Fifo underrun error
1’b0