PRELIMINARY
DRAM CONTROLLER
S3C6400X RISC MICROPROCESSOR
5-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PnT_RP
Bit
Description
Initial State
[31:6]
Read undefined. Write as Zero
scheduled_RP
[5:3]
Set the precharge to RAS delay in
aclk
cycles -3.
011
t_RP
[2:0]
Set the precharge to RAS delay in memory clock cycles
101
T_RRD REGISTER
Register
Address
R/W
Description
Reset Value
P0T_RRD
0x7E000034
R/W
16-bit DRAM controller t_RRD register
0x2
P1T_RRD
0x7E001034
R/W
32-bit DRAM controller t_RRD register
0x2
PnT_RRD
Bit
Description
Initial State
[31:4]
Read undefined. Write as Zero
t_RRD
[3:0]
Set Active bank x to Active bank y delay in memory clock cycles.
0x2
T_WR REGISTER
Register
Address
R/W
Description
Reset Value
P0T_WR
0x7E000038
R/W
16-bit DRAM controller t_WR register
0x3
P1T_WR
0x7E001038
R/W
32-bit DRAM controller t_WR register
0x3
PnT_WR
Bit
Description
Initial State
[31:3]
Read undefined. Write as Zero
t_WR
[2:0]
Set the write to precharge delay in memory clock cycles.
011
T_WTR REGISTER
Register
Address
R/W
Description
Reset Value
P0T_WTR 0x7E00003C
R/W 16-bit
DRAM
controller t_WTR register
0x2
P1T_WTR 0x7E00103C
R/W 32-bit
DRAM
controller t_WTR register
0x2
PnT_WTR
Bit
Description
Initial State
[31:3]
Read undefined. Write as Zero
t_WTR
[2:0]
Set the write to read delay in memory clock cycles.
010