Samsung S3C6400X, User Manual, Page: 978 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SPI CONTROLLER
29-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
0: no error, 1: underrun error
RxFifoRdy [1]
R
0 : data in FIFO less than trigger level
1 : data in FIFO more than trigger level
1’b0
TxFifoRdy [0]
R
0 : data in FIFO more than trigger level
1 : data in FIFO less than trigger level
1’b0
Register Address R/W Description Reset Value
SPI_TX_DATA(Ch0
)
0x7F00B018 W SPI TX DATA register 0x0
SPI_TX_DATA(Ch1
)
0x7F00C018 W SPI TX DATA register 0x0
SPI_TX_DATA Bit Description Initial State
TX_DATA [31:0]
W
This field contains the data to be transmitted
over the SPI channel. 32’b0
Register Address R/W Description Reset Value
SPI_RX_DATA(Ch0) 0x7F00B01C R SPI RX DATA register 0x0
SPI_RX_DATA(Ch1) 0x7F00C01C R SPI RX DATA register 0x0
SPI_RX_DATA Bit Description Initial State
RX_DATA [31:0]
R
This field contains the data to be received over
the SPI channel.
32’b0
Register Address R/W Description Reset Value
Packet_Count_reg(Ch0) 0x7F00B020 R/W Count how many data master gets 0x0
Packet_Count_reg(Ch1) 0x7F00C020 R/W Count how many data master gets 0x0
Packet_Count_reg Bit Description Initial State
Packet_Count_En [16]
R/W
Enable bit for packet count
0: Disable 1:Enable
1’b0
Count Value [15:0]
R/W Packet count value
16’b0