PRELIMINARY
SYSTEM CONTROLLER
S3C6400X RISC MICROPROCESSOR
3-30
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Clock gating control register
S3C6400 can disable the clock operation of each IP when it does not require running. The following three
registers control clock disable/enable operation.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HCLK_GATE 0x7E00_F030
R/W
HCLK
clock gating control
0xFFFF_FFFF
PCLK_GATE 0x7E00_F034
R/W
PCLK
clock gating control
0xFFFF_FFFF
SCLK_GATE 0x7E00_F038
R/W
Special clock gating control
0xFFFF_FFFF
HCLK_GATE controls HCLK of all IPs. If a field has ‘1’, then HCLK is supplied. Otherwise, HCLK is masked.
When S3C6400x goes to a power down mode, system controller checks the status of some block, IROM, MEM0,
MEM1, and MFC block. Therefore, bit 25, 22, 21, 0 should be ‘1’ to acknowledge a power down request.
HCLK_GATE
BIT
DESCRIPTION
RESET VALUE
RESERVED [31:30]
RESERVED
0x3
HCLK_UHOST
[29]
Gating HCLK for UHOST (0: mask, 1: pass)
1
HCLK_SECUR
[28]
Gating HCLK for security sub-system (0: mask, 1: pass)
1
HCLK_SDMA1
[27]
Gating HCLK for SDMA1 (0: mask, 1: pass)
1
HCLK_SDMA0
[26]
Gating HCLK for SDMA0 (0: mask, 1: pass)
1
HCLK_IROM
[25]
Gating HCLK for IROM (0: mask, 1: pass)
1
HCLK_DDR1
[24]
Gating HCLK for DDR1 (0: mask, 1: pass)
1
HCLK_DDR0
[23]
Gating HCLK for DDR0 (0: mask, 1: pass)
1
HCLK_MEM1
[22]
Gating HCLK for DMC1 (0: mask, 1: pass)
1
HCLK_MEM0 [21]
Gating HCLK for DMC0, SROM, OneNAND, NFCON,
CFCON (0: mask, 1: pass)
1
HCLK_USB
[20]
Gating HCLK for USB OTG (0: mask, 1: pass)
1
HCLK_HSMMC2
[19]
Gating HCLK for HSMMC2 (0: mask, 1: pass)
1
HCLK_HSMMC1
[18]
Gating HCLK for HSMMC1 (0: mask, 1: pass)
1
HCLK_HSMMC0
[17]
Gating HCLK for HSMMC0 (0: mask, 1: pass)
1
HCLK_MDP
[16]
Gating HCLK for MDP (0: mask, 1: pass)
1
HCLK_DHOST
[15]
Gating HCLK for direct HOST interface (0: mask, 1: pass)
1
HCLK_IHOST
[14]
Gating HCLK for indirect HOST interface (0: mask, 1: pass)
1
HCLK_DMA1
[13]
Gating HCLK for DMA1 (0: mask, 1: pass)
1
HCLK_DMA0
[12]
Gating HCLK for DMA0 (0: mask, 1: pass)
1
HCLK_JPEG
[11]
Gating HCLK for JPEG (0: mask, 1: pass)
1
HCLK_CAMIF
[10]
Gating HCLK for camera interface (0: mask, 1: pass)
1
HCLK_SCALER
[9]
Gating HCLK for scaler (0: mask, 1: pass)
1
HCLK_2D
[8]
Gating HCLK for 2D (0: mask, 1: pass)
1
HCLK_TV
[7]
Gating HCLK for TV encoder (0: mask, 1: pass)
1
RESERVED [6]
RESERVED
1