Samsung S3C6400X, User Manual, Page: 66 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER
3-21
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INDIVIDUAL REGISTER DESCRIPTIONS
PLL Control Registers
S3C6400 has three internal PLL’s, which are APLL, MPLL, and EPLL. They are controlled by the following seven
special registers.
REGISTER ADDRSS R/W DESCRIPTION RESET VALUE
APLL_LOCK 0x7E00_F000 R/W Control PLL locking period for APLL 0x0000_FFFF
MPLL_LOCK 0x7E00_F004 R/W Control PLL locking period for MPLL 0x0000_FFFF
EPLL_LOCK 0x7E00_F008 R/W Control PLL locking period for EPLL 0x0000_FFFF
APLL_CON 0x7E00_F00C R/W Control PLL output frequency for APLL 0x0190_0302
MPLL_CON 0x7E00_F010 R/W Control PLL output frequency for MPLL 0x0214_0603
EPLL_CON0 0x7E00_F014 R/W Control PLL output frequency for EPLL 0x0020_0102
EPLL_CON1 0x7E00_F018 R/W Control PLL output frequency for EPLL 0x0000_9111
A PLL requires locking period when input frequency is changed or frequency division (multiplication) values are
changed. PLL_LOCK register specifies this locking period, which is based on PLL’s source clock. During this
period, output will be masked ‘0’.
APLL_LOCK /
MPLL_LOCK /
EPLL_LOCK
BIT DESCRIPTION RESET VALUE
RESERVED [31:16] RESERVED 0x0000
PLL_LOCKTIME [15:0] Required period to generate a stable clock output 0xFFFF
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates
output after PLL locking period. The output frequency of PLL is controlled by the MDIV, PDIV, SDIV, and KDIV
values. APLL_LOCK, MPLL_LOCK, and EPLL_LOCK fields denote the number of external clock. User can adjust
this fields which must be larger than 300us.
APLL_CON /
MPLL_CON
BIT DESCRIPTION RESET VALUE
ENABLE [31] PLL enable control (0: disable, 1: enable) 0
RESERVED [30:26] RESERVED 0x00
MDIV [25:16] PLL M divide value 0x190 / 0x214
RESERVED [15:14] RESERVED 0x0
PDIV [13:8] PLL P divide value 0x3 / 0x6
RESERVED [7:3] RESERVED 0x00
SDIV [2:0] PLL S divide value 0x2 / 0x3
The reset value of APLL_CON / MPLL_CON generate 400MHz and 133MHz output clock respectively, if the input
clock frequency is 12MHz.