Samsung S3C6400X, User Manual, Page: 72 / 1189

PRELIMINARY
S3C6400X RISC MICROPROCESSOR SYSTEM CONTROLLER
3-27
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Clock divider control register
S3C6400 has several clock dividers to support various operating clock frequency. The clock divider ratio can be
controlled by CLK_DIV0, CLK_DIV1, and CLK_DIV2.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
CLK_DIV0 0x7E00_F020 R/W Set clock divider ratio 0x0105_1000
CLK_DVI1 0x7E00_F024 R/W Set clock divider ratio 0x0000_0000
CLK_DIV2 0x7E00_F028 R/W Set clock divider ratio 0x0000_0000
CLK_DIV0 mainly controls the system clocks and special clocks of multimedia IPs. The output frequencies of
APLL and MPLL are divided by ARM_RATIO and MPLL_RATIO. HCLKX2 clock is the base clock of other
operating system clocks and divided by HCLKX2_RATIO. There is operating frequency limitation. The maximum
operating frequency of HCLKX2, HCLK, and PCLK are 266MHz, 133MHz, and 66MHz, respectively. NAND,
SECUR, JPEG operating clock cannot exceed 66MHz. MFC and CAM operating clock cannot exceed 133MHz.
This operating clock condition must be met through CLK_DIV0 configuration.
User software must be care for the clock divider controlled by CLK_DIV0. Since the output frequency will be
varying during the clock ratio-changing period as shown in Figure 3-6.
CLK_DIV0 BIT DESCRIPTION RESET VALUE
MFC_RATIO [31:28]
MFC clock divider ratio
CLKMFC = CLKMFC
IN
/ ( MFC 1 )
0x0
JPEG_RATIO [27:24]
JPEG clock divider ratio, which must be odd value. In other
words, S3C6400 supports only even divider ratio.
CLKJPEG = HCLKX2 / (JPEG 1)
0x1
CAM_RATIO [23:20]
CAM clock divider ratio
CLKCAM = HCLKX2 / (CAM 1)
0x0
SECUR_RATIO [19:18]
Security clock divider ratio, which must be 0x1 or 0x3.
CLKSECUR = HCLKX2 / (SECUR 1)
0x1
RESERVED [17:16] RESERVED 0x1
PCLK_RATIO [15:12]
PCLK clock divider ratio, which must be odd value. In other
words, S3C6400 supports only even divider ratio.
PCLK = HCLKX2 / (PCLK 1)
0x1
HCLKX2_RATIO [11:9]
HCLKX2 clock divider ratio
HCLKX2 = HCLKX2
IN
/ (HCLKX2 1)
0x0
HCLK_RATIO [8]
HCLK clock divider ratio
HCLK = HCLKX2 / (HCLK 1)
0
RESERVED [7:5] RESERVED 0x0
MPLL_RATIO [4]
DIV
MPLL
clock divider ratio
DOUT
MPLL
= MOUT
MPLL
/ (MPLL 1)
0
RESERVED [3] RESERVED 0