Samsung S3C6400X, User Manual, Page: 1001 / 1189

PRELIMINARY
UART S3C6400 RISC MICROPROCESSOR
31-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 31-1 Interrupts in Connection with FIFO
UART ERROR STATUS FIFO
UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data,
among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has
an error, is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be
read out.
For example:
It is assumed that the UART Rx FIFO receives A, B, C, D,and E characters sequentially and the frame error
occurs while receiving 'B', and the parity error occurs while receiving 'D'.
The actual UART receive error will not generate any error interrupt because the character, which was received
with an error, has not been read yet. The error interrupt will occur when the character is read out.
Figure 31-3 shows the UART receiving the five characters including the two errors.
Type FIFO Mode Non-FIFO Mode
Rx interrupt Generated whenever receive data reaches the
trigger level of receive FIFO.
Generated when the number of data in FIFO does
not reaches Rx FIFO trigger Level and does not
receive any data during 3 word time (receive time
out). This interval follows the setting of Word
Length bit. Generated by the receive holding register
whenever receive buffer becomes full.
Tx interrupt Generated whenever transmit data reaches the
trigger level of transmit FIFO (Tx FIFO trigger
Level). Generated by the transmit holding
register whenever transmit buffer is
empty.
Error interrupt Generated when frame error, parity error, or break
signal are detected.
Generated when it gets to the top of the receive
FIFO without reading out data in it (overrun error).
Generated by all errors. However if
another error occurs at the same time,
only one interrupt is generated.